Description
ColdFire Core Enhanced Multiply-Accumulate Unit (EMAC)
Memory Management Unit (MMU) Floating-Point Unit (FPU) Local Memory Debug Support
System Integration Unit (SIU) Internal Clocks and Bus Architecture
General Purpose Timers (GPT) Slice Timers (SLT)
Interrupt Controller (INTC) Edge Port Module (EPORT) General Purpose I/O (GPIO)
System SRAM FlexBus
SDRAM Controller (SDRAMC) PCI Bus Controller (PCI)
PCI Bus Arbiter (PCIARB) Integrated Secuity Engine (SEC) IEEE 1149.1 Test Access Port (JTAG)
Mul
Features
- 1-3
1.4.1 ColdFire V4e Core Overview  1-5 1.4.2 Debug Module (BDM)  1-6 1.4.3 JTAG  1-6 1.4.4 On-Chip Memories  1-7 1.4.5 PLL and Chip Clocking Options  1-7 1.4.6 Communications I/O Subsystem  1-8 1.4.7 DDR SDRAM Memory Controller  1-10 1.4.8 Peripheral Component Interconnect (PCI)  1-10 1.4.9 Flexible Local Bus (FlexBus)  1-10 1.4.10 Security Encryption Controller (SEC)  1-11 1.4.11 System Integration Unit (SIU)  1-11
Chapter 2 Signal.