MB91355A
MB91355A is (MB91F35xA) 32-Bit Proprietary Microcontroller manufactured by Fujitsu Semiconductor Limited.
- Part of the MB91F354A comparator family.
- Part of the MB91F354A comparator family.
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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-16504-3E
32-Bit Proprietary Microcontroller
CMOS
FR60 MB91350A Series
MB91F355A/F356B/355A/354A/V350A
- DESCRIPTION
The FR families are lines of standard single-chip microcontrollers each based on a 32-bit high-performance RISC CPU, incorporating a variety of I/O resources and bus control Features for embedded control applications which require high CPU performance for This FR60 family is based on FR30 and FR40 families and enhanced is bus access. The FR60 family is a line of single-chip oriented microcontrollers incorporating a wealth of peripheral resources. The FR60 family is optimized for embedded control applications requiring high processing power of the CPU, such as DVD player, navigation, high performance Fax machine, and printer controls.
- Features
1. FR CPU
32-bit RISC, load/store architecture with a five-stage pipeline Maximum operating frequency: 50 MHz (using the PLL at an oscillation frequency of 12.5 MHz) 16-bit fixed length instructions (basic instructions), 1 instruction per cycle Instruction set optimized for embedded applications: Memory-to-memory transfer, bit manipulation, barrel shift etc.
- Instructions adapted for high-level languages: Function entry/exit instructions, multiple-register load/store instructions (Continued)
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- PACKAGE
176-pin plastic LQFP
(FPT-176P-M02)
I2C license Purchase of Fujitsu I2C ponents conveys a license under the Philips I2C Patent Rights to use, these ponents in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips.
Data Sheet 4 U .
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MB91350A Series
- Register interlock functions: Facilitating coding in assemblers
- On-chip multiplier supported at the instruction level. Signed 32-bit multiplication: 5 cycles. Signed 16-bit multiplication: 3 cycles
- Interrupt (PC, PS save): 6 cycles, 16 priority levels
- Harvard architecture allowing program access and data access...