Description
Preliminary GS8342T08/09/18/36E-333/300/267 */250/200/167 165-Bump BGA Commercial Temp Industrial Temp .
Table Symbol
SA NC R/W BW0.
BW3 NW0.
NW1 LD K K C C TMS TDI TCK TDO VREF ZQ DQ Doff CQ CQ VDD VDDQ VSS Note: NC = Not Connected to die o.
Features
* Simultaneous Read and Write SigmaCIO™ Interface
* Common I/O bus
* JEDEC-standard pinout and package
* Double Data Rate interface
* Byte Write (x36 and x18) and Nybble Write (x8) function
* Burst of 2 Read and Write
* 1.8 V +100/
* 100
Applications
* Therefore, the SigmaCIO DDR-II SRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs are unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high speed Common I/O SRAM data bandwidth in half. Burst Operat
