Description
200 MHz
333 MHz 1.8 V VDD 1.8 V I/O
SigmaRAM Family Overview
GS8170LW36/72 SigmaRAMs are built in compliance with the SigmaRAM pinout standard for synchronous SRAMs.They are 18,874,368-bit (18Mb) SRAMs.This family of wide, very low voltage CMOS I/O SRAMs is designed to operate at the speeds needed to implement economical high performance networking systems.Bottom View
209-Bump, 14 mm x 22 mm BGA 1 mm Bump Pitch, 11 x 19 Bump Array
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ΣRAMs are offered in a number
Features
- Late Write mode, Pipelined Read mode.
- JEDEC-standard SigmaRAM™ pinout and package.
- 1.8 V +150/.
- 100 mV core power supply.
- 1.8 V CMOS Interface.
- ZQ controlled user-selectable output drive strength.
- Dual Cycle Deselect.
- Burst Read and Write option.
- Fully coherent read and write pipelines.
- Echo Clock outputs track data output drivers.
- Byte write operation (9-bit bytes).
- 2 user-programmable chi.