GS8161E18 - (GS8161E18 - GS8161E36) Sync Burst SRAMs

GSI

GS8161E18 Datasheet Preview — Preview of GS8161E18 PDF

Datasheet Details

Part number	GS8161E18
Manufacturer	GSI
File Size	936.23 KB
Description	(GS8161E18 - GS8161E36) Sync Burst SRAMs
Datasheet	GS8161E18_GSI.pdf

GS8161E18 Product details

Description

Applications The GS8161E18(T/D)/GS8161E32(D)/GS8161E36(T/D) is a 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter.Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one

Features

FT pin for user-configurable flow through or pipeline operation.
Dual Cycle Deselect (DCD) operation.
IEEE 1149.1 JTAG-compatible Boundary Scan.
2.5 V or 3.3 V +10%/.
10% core power supply.
2.5 V or 3.3 V I/O supply.
LBO pin for Linear or Interleaved Burst mode.
Internal input resistors on mode pins allow floating mode pins.
Default to Interleaved Pipeline mode.
Byte Write (BW) and/or Global Write (GW) opera.

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Published: Feb 9, 2007 |