Description
Table
Symbol
Description
SA Synchronous Address Inputs
NC No Connect
R Synchronous Read
W Synchronous Write
BW0
BW1
Synchronous Byte Writes
BW2
BW3
Synchronous Byte Writes
K Input Clock
K Input Clock
C Output Clock
C Output Clock
TMS Test Mode Select
TDI Test Data Input
TCK Test Clock Input
TDO Test Data Output
VREF HSTL Input Reference Voltage
ZQ Output Impedance Matching Input
MCL Must Connect Low
D0
D17
Synchronous Data Inputs
D18
D35
S
Features
- Simultaneous Read and Write SigmaQuad™ Interface.
- JEDEC-standard pinout and package.
- Dual DoubleData Rate interface.
- Byte Write controls sampled at data-in time.
- Burst of 2 Read and Write.
- 2.5 V +100/.
- 100 mV core power supply.
- 1.5 V or 1.8 V HSTL Interface.
- Pipelined read operation.
- Fully coherent read and write pipelines.
- ZQ mode pin for programmable output drive strength.
- IEEE 1149.1 JTA.