H5TQ4G63CFR-xxL
Description
The H5TQ4G83CFR-xxC,H5TQ4G63CFR-xxC, H5TQ4G83CFR-xxI, H5TQ4G63CFR-xxI, H5TQ4G83CFR-xxL, H5TQ4G63CFR-xxL,H5TQ4G83CFR-xxJ and H5TQ4G63CFR-xxJ are a 4,294,967,296-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth.
Key Features
- VDD=VDDQ=1.5V +/- 0.075V
- Fully differential clock inputs (CK, CK) operation
- Differential Data Strobe (DQS, DQS)
- On chip DLL align DQ, DQS and DQS transition with CK transition
- DM masks write data-in at the both rising and falling edges of the data strobe
- All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
- Programmable additive latency 0, CL-1, and CL-2 supported
- Programmable burst length 4/8 with both nibble sequential and interleave mode
- BL switch on the fly
- Average Refresh Cycle (Tcase of0 oC~95oC)
