H5TQ4G63MFR-xxJ Datasheet | SK Hynix

Description The H5TQ4G83MFR-xx C,H5TQ4G63MFR-xx C, H5TQ4G83MFR-xx I, H5TQ4G63MFR-xx I, H5TQ4G83MFR-xx J and H5TQ4G63MFR-xx J are a 4,294,967,296-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. Hynix 4Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth. Device Features and Ordering Information FEATURES - VDD=VDDQ=1.5V +/- 0.075V - Fully differential clock inputs (CK, CK) operation - Differential Data Strobe (DQS, DQS) - On chip DLL align DQ, DQS and DQS transition with CK transition - DM masks write data-in at the both rising and falling edges of the data strobe - All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock - 8banks - Average Refresh Cycle (Tcase of 0 o C~ 95 o C) - 7.8 µs at 0o C ~ 85 o C - 3.9 µs at 85o C ~ 95 o C mercial Temperature( 0o C ~ 85 o C) Industrial Temperature( -40o C ~ 95 o C) - Auto Self Refresh supported - JEDEC standard 78ball FBGA(x8), 96ball FBGA (x16) - Driver strength selected by EMRS - Programmable CAS latency 5, 6, 7, 8, 9, 10 and 11, 13 - Dynamic On Die Termination supported supported - Asynchronous RESET pin supported - Programmable additive latency 0, CL-1, and CL-2 supported - Programmable CAS Write latency (CWL) = 5, 6, 7, 8 - Programmable burst length 4/8 with both nibble sequential and interleave mode - BL switch on the fly - ZQ calibration supported - TDQS (Termination Data Strobe) supported (x8 only) - Write Levelization supported - 8 bit pre-fetch - This product in pliance with the Ro HS...