HYMP532S64CP6-E3 Datasheet (Hynix) - 200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 512 Mb

HYMP532S64CP6-E3, 200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 512 Mb

and is subject to change without notice.

Hynix Semiconductor does not assume any responsibility for use of circuits described.

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Rev.

0.4 / Jul.

2007 1 1200pin Unbuffered DDR2 SDRAM SO-DIMMs SPEED GRADE & KEY PARAMETERS E3 (DDR2-400) Speed @CL3 Speed @CL4 Speed @CL5 Sp

HYMP532S64CP6-E3 Features

* JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface Posted CAS Programmable CAS Latency 3, 4, 5, 6 OCD (Off-Chip Driver Impedance Adjustment) and ODT (On-Die Termination) Fully differ