9FGL0651 Features
* ▪ Six 100MHz Low-Power HCSL (LP-HCSL) DIF pairs:
* 9FGL0641 default Zo = 100Ω
* 9FGL0651 default Zo = 85Ω ▪ One 3.3V LVCMOS REF output with Wake-On-LAN (WOL) support ▪ See AN-891 for easy AC-coupling to other logic families Key Specifications ▪ PCIe Gen1
* 4 CC compliant; Gen2
Datasheet Details
9FGL0651, 9FGL0641
IDT
319.72 KB
6-output 3.3v pcie clock generator.
This datasheet PDF includes multiple part numbers: 9FGL0651, 9FGL0641.
Please refer to the document for exact specifications by model.
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9FGL0651 Distributor
