IS61DDP2B41M18C - 18Mb DDR-IIP CIO SYNCHRONOUS SRAM

ISSI

IS61DDP2B41M18C Datasheet Preview — Preview of IS61DDP2B41M18C PDF

Datasheet Details

Part number	IS61DDP2B41M18C
Manufacturer	ISSI
File Size	1.05 MB
Description	18Mb DDR-IIP CIO SYNCHRONOUS SRAM
Datasheet	IS61DDP2B41M18C-ISSI.pdf

IS61DDP2B41M18C Product details

Description

512Kx36 and 1Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window. Common I/O read and write ports. Synchronous pipeline read with self-timed late write operation. Double Data Rate (DDR) interface for read and write input ports. 2.0 cycle read latency. Fixed 4-bit burst for read and write operations. Clock stop support. Two input clocks (K and K#) for address and control registering at rising edges only.

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Published: Feb 18, 2024 |