* Internal self-timed write cycle
* Individual Byte Write Control and Global Write
* Clock controlled, registered address, data and control
* Burst sequence control using MODE input
* Three chip enable option for simple depth ex- pansion and address pipelini
IS61VVPS51218B Datasheet (1.00 MB)
IS61VVPS51218B
ISSI
1.00 MB
9mb single cycle deselect static ram.
IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B
256K x 36, 256K x 32, 512K x 18 9 Mb SYNCHRONOUS P.
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