Click to expand full text
HYB39S256400/800/160CT(L) 256MBit Synchronous DRAM
256 MBit Synchronous DRAM
•
High Performance:
-7.5 fCK tCK3 tAC3 tCK2 tAC2 133 7.5 5.4 10 6 -8 125 8 6 10 6 Units MHz ns ns ns ns
• • • • • • • • • • • •
Multiple Burst Read with Single Write Operation Automatic Command and Controlled Precharge
Data Mask for Read / Write control (x4, x8) Data Mask for byte control (x16) Auto Refresh (CBR) and Self Refresh Power Down and Clock Suspend Mode 8192 refresh cycles / 64 ms (7,8 µs) Random Column Address every CLK ( 1-N Rule) Single 3.3V +/- 0.3V Power Supply LVTTL Interface versions Plastic Packages: P-TSOPII-54 400mil width (x4, x8, x16) -7.
HYB39S256800CT Datasheet
