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HYB39S256400/800/160DT(L)/DC(L) 256MBit Synchronous DRAM
256 MBit Synchronous DRAM
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High Performance:
-6 fCK tCK3 tAC3 tCK2 tAC2 166 6 5 7.5 5.4 -7 143 7 5.4 7.5 5.4 -7.5 133 7.5 5.4 10 6 -8 125 8 6 10 6 Units MHz ns ns ns
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Data Mask for Read / Write control (x4, x8) Data Mask for byte control (x16) Auto Refresh (CBR) and Self Refresh Power Down and Clock Suspend Mode 8192 refresh cycles / 64 ms (7,8 µs) Random Column Address every CLK ( 1-N Rule) Single 3.3V +/- 0.3V Power Supply LVTTL Interface versions Plastic Packages: P-TSOPII-54 400mil width (x4, x8, x16) Chipsize Packages: 54 ball TFBGA (12 mm x 8 mm) -6 parts for PC166 3-3-3 operation -7 parts for PC133 2-2-2 operation -7.
HYB39S256800DTL Datasheet
