* High Performance 16-bit CPU with 4-Stage Pipeline
* 80 ns Instruction Cycle Time at 25 MHz CPU Clock
* 400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit)
* Enhanced Boolean Bit Manipulation Facilities
* Additional Instructions to Support HLL and Operat
C161S
1.28 MB
16-bit single-chip microcontroller.
D a t a S h e e t , V 1. 0 , N o v . 20 0 3 C161S 1 6 - B i t S i n g l e - C h i p M i c r o c o n t r o l l er M i c r o c o n t r o l l er s N e.
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