ESD102-U4-05L Datasheet - Infineon

ESD102-U4-05L Transient Voltage Suppressor Diodes

Pin 5 Pin 4 Pin 1 Pin 3 Pin 4 Pin 5 I/O I/O I/O I/O Pin 1 Pin 2 Pin 3 a) Pin configuration GND Pin 2 b) Schematic diagram Figure 1 Pin Configuration and Schematic Diagram Table 1 Ordering Information Type Package ESD102-U4-05L TSLP-5-2 Configuration 4 lines, uni-directional Final Data Sh.

TVS Diodes Transient Voltage Suppressor Diodes ESD102-U4-05L Ultra-Low Capacitance ESD Protection Array for Flow-Through PCB Layout ESD102-U4-05L Data Sheet Revision 1.0, 2013-02-25 Final Power Management & Multimarket Edition 2013-02-25 Published by Infineon Technologies AG 81726 Munich, Germany © 2013 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect .

ESD102-U4-05L Features

* ESD / transient protection of high speed data lines exceeding:

* IEC61000-4-2 (ESD): ±24 kV (air), ±20 kV (contact)

* IEC61000-4-4 (EFT): ±60 A / ±3 kV (5/50ns)

* IEC61000-4-5 (Surge): ±3.5 A (8/20μs)

* Maximum working voltage: VRWM = 3.3 V

* Ultra l

ESD102-U4-05L Datasheet (1.35 MB)