S26KS128S - 128Mb (16MB) HYPER FLASH
1.1 DDR center aligned read strobe (DCARS) functionality 7 1.2 Error detection and correction functionality 7 2 Connection diagram10 2.1 FBGA 24-ball 5 × 5 array footprint 10 3 Signal description 11 4 HYPERBUS™ protocol
S26KS128S Features
* 3.0 V I/O, 11 bus signals - Single ended clock
* 1.8 V I/O, 12 bus signals - Differential clock (CK, CK#)
* Chip Select (CS#)
* 8-bit data bus (DQ[7:0])
* Read-write data strobe (RWDS) - HYPERFLASH™ memories use RWDS only as a Read Data Strobe
* Up t