S27KL0642 - 64Mb self-refresh DRAM
1.1 HYPERBUS™ interface5 2 Product overview 8 2.1 HYPERBUS™ interface8 3 Signal description 9 3.1 Input/output summary9 4 HYPERBUS™ transaction details 10 4.1 Command/address bit assignments10 4.2 Read transactions 15 4.3 Write transactions (Memory array write)16 4.4 Write transactions without init
S27KL0642 Features
* Interface - HYPERBUS™ interface - 1.8 V / 3.0 V interface support
* Single-ended clock (CK) - 11 bus signals
* Optional differential clock (CK, CK#) - 12 bus signals - Chip select (CS#) - 8-bit data bus (DQ[7:0]) - Hardware reset (RESET#) - Bidirectional read-write data str
