* such as posted CAS# with additive latency, Write latency = Read latency -1, Off-Chip Driver (OCD) impedance adjustment, and On Die Termination (ODT). All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point
NDB16P
Insignis
1.60 MB
1gb (x16) - ddr2 synchronous dram.
1Gb (x16)
* DDR2 Synchronous DRAM
64M x 16 bit DDR2 Synchronous DRAM
Overview
The NDB16P is a high-speed CMOS Double-Data-Rate-Two (DDR2), s.
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