IDT54FCT88915TT - LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)

Integrated Device

Datasheet Details

Part number	IDT54FCT88915TT
Manufacturer	Integrated Device
File Size	140.51 KB
Description	LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)
Datasheet	IDT54FCT88915TT_IntegratedDeviceTechnology.pdf

The IDT54/74FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock.

0.5 MICRON CMOS Technology.
Input frequency range: 10MHz.
f2Q Max. spec (FREQ_SEL = HIGH).
Max. output frequency: 133MHz.
Pin and function compatible with MC88915T.
5 non-inverting outputs, one inverting output, one 2x output, one ÷ 2 output; all outputs are TTL-compatible.
3-State outputs.
Output skew < 500ps (max. ).
Duty cycle distortion < 500ps (max. ).
Part-to-part skew: 1ns (from tPD max. spec).

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Published: Apr 27, 2005 |