Datasheet Details
| Part number | IS61DDB41M18A |
|---|---|
| Manufacturer | Integrated Silicon Solution |
| File Size | 469.90 KB |
| Description | 18Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM |
| Datasheet |
 IS61DDB41M18A-IntegratedSiliconSolution.pdf
|
| Part number | IS61DDB41M18A |
|---|---|
| Manufacturer | Integrated Silicon Solution |
| File Size | 469.90 KB |
| Description | 18Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM |
| Datasheet |
IS61DDB41M18A-IntegratedSiliconSolution.pdf
|
512Kx36 and 1Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid window. Common I/O read and write ports. Synchronous pipeline read with late write operation. Double Data Rate (DDR) interface for read and write input ports. Fixed 4-bit burst for read and write operations. Clock stop support. Two input clocks (K and K#) for address and control registering at rising edges only. Two input clocks (C and C#) for data
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