IS61DDB41M18A Datasheet - Integrated Silicon Solution

18Mb DDR-II (Burst 4) CIO SYNCHRONOUS SRAM

IS61DDB41M18A General Description

* 512Kx36 and 1Mx18 configuration available. * On-chip delay-locked loop (DLL) for wide data valid window. * Common I/O read and write ports. * Synchronous pipeline read with late write operation. * Double Data Rate (DDR) interface for read and write input ports. * Fixed 4-b.

IS61DDB41M18A Datasheet (469.90 KB)

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IS61DDB41M18A

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Integrated Silicon Solution

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18mb ddr-ii (burst 4) cio synchronous sram.

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IS61DDB41M18A 18Mb DDR-II Burst CIO SYNCHRONOUS SRAM Integrated Silicon Solution

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IS61DDB41M18A General Description

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