* DESCRIPTION
* 2Mx36 and 4Mx18 configuration available.
* On-chip Delay-Locked Loop (DLL) for wide data valid window.
* Common I/O read and write ports.
* Synchronous pipeline read with self-timed late write operation.
* Double Data Rate (DDR) interface for read and write input
IS61DDPB42M36A1 Datasheet (528.87 KB)
IS61DDPB42M36A1
Integrated Silicon Solution
528.87 KB
72mb ddr-iip(burst 4) cio synchronous sram.
IS61DDPB44M18A/A1/A2 IS61DDPB42M36A/A1/A2
4Mx18, 2Mx36 72Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM
(2.5 Cycle Read Latency)
ADVANCED INFORMATION JULY .
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