IS61DDPB24M18C1, IS61DDPB24M18C - 72Mb DDR-IIP CIO SYNCHRONOUS SRAM

ISSI

Datasheet Details

Part number	IS61DDPB24M18C1, IS61DDPB24M18C
Manufacturer	ISSI
File Size	851.41 KB
Description	72Mb DDR-IIP CIO SYNCHRONOUS SRAM
Datasheet	IS61DDPB24M18C-ISSI.pdf
Note	This datasheet PDF includes multiple part numbers: IS61DDPB24M18C1, IS61DDPB24M18C. Please refer to the document for exact specifications by model.

at page 6 for each ODT option.

2Mx36 and 4Mx18 configuration available.
Common I/O read and write ports.
Max. 567 MHz clock for high bandwidth.
Synchronous pipeline read with self-timed late write operation.
Double Data Rate (DDR) interface for read and write input ports.
2.5 cycle read latency.
Fixed 2-bit burst for read and write operations.
Two input clocks (K and K#) for address and control registering at rising edges only.
Two echo clocks (CQ and CQ#) that are delivere.

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Published: Feb 18, 2024 |