IS61DDPB24M18C1 - 72Mb DDR-IIP CIO SYNCHRONOUS SRAM
at page 6 for each ODT option.
DESCRIPTION The 72Mb IS61DDPB22M36C/C1/C2 and IS61DDPB24M18 C/C1/C2 are synchronous, high-performance CMOS static random access memory (SRAM) devices.
These SRAMs have a common I/O bus.
The rising edge of K clock initiates the read/write operation, and all internal op
IS61DDPB24M18C1 Features
* 2Mx36 and 4Mx18 configuration available.
* Common I/O read and write ports.
* Max. 567 MHz clock for high bandwidth
* Synchronous pipeline read with self-timed late write operation.
* Double Data Rate (DDR) interface for read and write input ports.
* 2.5 cycle read latency.
