* 2Mx36 and 4Mx18 configuration available.
* On-chip Delay-Locked Loop (DLL) for wide data valid window.
* Common I/O read and write ports.
* Synchronous pipeline read with self-timed late write operation.
* Double Data Rate (DDR) interface for read and write input ports.
*
IS61DDPB24M18A-IntegratedSiliconSolution.pdf
Datasheet Details
IS61DDPB24M18A2, IS61DDPB24M18A
Integrated Silicon Solution
509.16 KB
72mb ddr-iip(burst 2) cio synchronous sram.
This datasheet PDF includes multiple part numbers: IS61DDPB24M18A2, IS61DDPB24M18A.
Please refer to the document for exact specifications by model.
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