| Part number | IS61DDPB24M18B1, IS61DDPB24M18B |
|---|---|
| Manufacturer | Integrated Silicon Solution |
| File Size | 932.26 KB |
| Description | 72Mb DDR-IIP CIO SYNCHRONOUS SRAM |
| Datasheet |
 IS61DDPB24M18B-IntegratedSiliconSolution.pdf
|
| Note |
This datasheet PDF includes multiple part numbers: IS61DDPB24M18B1, IS61DDPB24M18B. Please refer to the document for exact specifications by model. |
2Mx36 and 4Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window. Common I/O read and write ports. Synchronous pipeline read with self-timed late write operation. Double Data Rate (DDR) interface for read and write input ports. 2.5 cycle read latency. Fixed 2-bit burst for read and write operations. Clock stop support. Two input clocks (K and K#) for address and control registering at rising edges only.
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