Part number:
IS61DDPB24M18
Manufacturer:
Integrated Silicon Solution
File Size:
572.22 KB
Description:
Ddr-iip (burst of 2) cio synchronous srams.
* 2M x 36 or 4M x 18.
* On-chip delay-locked loop (DLL) for wide data valid window.
* Common data input/output bus.
* Synchronous pipeline read with self-timed late write operation.
* Double data rate (DDR-IIP) interface for read and write input ports.
IS61DDPB24M18 Datasheet (572.22 KB)
IS61DDPB24M18
Integrated Silicon Solution
572.22 KB
Ddr-iip (burst of 2) cio synchronous srams.
📁 Related Datasheet
IS61DDPB24M18A 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM (Integrated Silicon Solution)
IS61DDPB24M18A1 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM (Integrated Silicon Solution)
IS61DDPB24M18A2 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM (Integrated Silicon Solution)
IS61DDPB24M18B 72Mb DDR-IIP CIO SYNCHRONOUS SRAM (Integrated Silicon Solution)
IS61DDPB24M18B1 72Mb DDR-IIP CIO SYNCHRONOUS SRAM (Integrated Silicon Solution)
IS61DDPB24M18B2 72Mb DDR-IIP CIO SYNCHRONOUS SRAM (Integrated Silicon Solution)
IS61DDPB24M18C 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM (ISSI)
IS61DDPB24M18C1 72Mb DDR-IIP CIO SYNCHRONOUS SRAM (ISSI)
IS61DDPB24M18C2 72Mb DDR-IIP CIO SYNCHRONOUS SRAM (ISSI)
IS61DDPB21M18A 18Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM (Integrated Silicon Solution)