IS61DDPB24M18 - DDR-IIP (Burst of 2) CIO Synchronous SRAMs

Integrated Silicon Solution

Datasheet Details

Part number	IS61DDPB24M18
Manufacturer	Integrated Silicon Solution
File Size	572.22 KB
Description	DDR-IIP (Burst of 2) CIO Synchronous SRAMs
Datasheet	IS61DDPB24M18-IntegratedSiliconSolution.pdf

The 72Mb IS61DDPB22M36 and IS61DDPB24M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices.

2M x 36 or 4M x 18.
On-chip delay-locked loop (DLL) for wide data valid window.
Common data input/output bus.
Synchronous pipeline read with self-timed late write operation.
Double data rate (DDR-IIP) interface for read and write input ports.
Fixed 2-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K) for address and control registering at rising edges only.
Industrial te.

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Published: Jul 25, 2016 |