Datasheet Details
| Part number | IS61DDPB21M18A |
|---|---|
| Manufacturer | Integrated Silicon Solution |
| File Size | 509.49 KB |
| Description | 18Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM |
| Datasheet |
 IS61DDPB21M18A-IntegratedSiliconSolution.pdf
|
| Part number | IS61DDPB21M18A |
|---|---|
| Manufacturer | Integrated Silicon Solution |
| File Size | 509.49 KB |
| Description | 18Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM |
| Datasheet |
IS61DDPB21M18A-IntegratedSiliconSolution.pdf
|
512Kx36 and 1Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window. Common I/O read and write ports. Synchronous pipeline read with self-timed late write operation. Double Data Rate (DDR) interface for read and write input ports. 2.5 cycle read latency. Fixed 2-bit burst for read and write operations. Clock stop support. Two input clocks (K and K#) for address and control registering at rising edges only.
📁 IS61DDPB21M18A Similar Datasheet