Datasheet4U Logo Datasheet4U.com

E8870SP - Scalability Port Switch

Datasheet Summary

Description

at any time, without notice.

Features

  • s s s Scalability Port (SP):.
  • Six SPs with 3.2 GB/s peak bandwidth per direction per SP.
  • Bi-directional SPs for a total bandwidth of 38.4 GB/s. Integrated Snoop Filter:.
  • 1 MB 12-way set associative tag array capable of maintaining state of 200K cache lines.
  • Partitioned into four interleaves, each interleave can be accessed in parallel.
  • Supports up to 266M look-up and update (LUU) operations per second.
  • Pseudo Least Recently Used (PLRU).

📥 Download Datasheet

Datasheet preview – E8870SP

Datasheet Details

Part number E8870SP
Manufacturer Intel Corporation
File Size 1.60 MB
Description Scalability Port Switch
Datasheet download datasheet E8870SP Datasheet
Additional preview pages of the E8870SP datasheet.

📁 Similar Datasheet

  • E88C - UHF Triode (Siemens)
  • E88C - S.Q. Tube (Philips)
  • E88C - Special Quality Triode (Philips)
  • E88CC - Trioda (ETC)
  • E88CC - Doppeltriode (Siemens)
  • E88CC - High Gain Twin Triode (AEG)
  • E88CC - Special Quality Double Triode (Philips)
  • E88CC - R. F. DOUBLE TRIODE (JJ)
  • E88CC - Twin Triode (TELEFUNKEN)
  • E88CC - S.Q. Tube (Philips)
Other Datasheets by Intel Corporation
  • E8870 - Intel E8870 Scalable Node Controller
  • E8870DH - Intel E8870DH DDR Memory Hub
  • E8870IO - Intel E8870IO Server I/o Hub

Full PDF Text Transcription

Click to expand full text
www.DataSheet4U.com Intel® E8870SP Scalability Port Switch (SPS) Datasheet Product Features s s s Scalability Port (SP): — Six SPs with 3.2 GB/s peak bandwidth per direction per SP. — Bi-directional SPs for a total bandwidth of 38.4 GB/s. Integrated Snoop Filter: — 1 MB 12-way set associative tag array capable of maintaining state of 200K cache lines. — Partitioned into four interleaves, each interleave can be accessed in parallel. — Supports up to 266M look-up and update (LUU) operations per second. — Pseudo Least Recently Used (PLRU) replacement algorithm, with updates on look-ups and invalidates. — ECC coverage, with correction of single bit errors, detection of double bit errors. — Fast array initialization and/or self test through configuration register access.
Published: |