X5083 Datasheet - Intersil Corporation

X5083 CPU Supervisor

PIN (SOIC/ PDIP) 1 PIN TSSOP 3 NAME CS/WDI FUNCTION Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the device, placing it in the active p.

® X5083 Data Sheet June 15, 2006 FN8127.3 CPU Supervisor with 8Kbit SPI EEPROM This device combines four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power-on reset circuit which holds RESET active for a period of time. This allows the power supply and oscillator.

X5083 Features

* Low VCC detection and reset assertion - Four standard reset threshold voltages 4.63V, 4.38V, 2.93V, 2.63V - Re-program low VCC reset threshold voltage using special programming sequence - Reset signal valid to VCC = 1V

* Selectable time out watchdog timer

* Long battery lif

X5083 Datasheet (346.01 KB)