Description
ispClock 5400D Family ™ In-System Programmable, Ultra-Low Jitter Zero Delay and Fan-Out Buffer, Differential November 2009 Preliminary Data Sheet DS1.
The ispClock5400D family integrates a CleanClock PLL and a FlexiClock Output block.
Features
* CleanClock™ PLL
* Ultra Low Period Jitter 2.5ps
* Ultra Low Phase Jitter 6.5ps
* Fully Integrated High-Performance PLL
* Programmable lock detect Four output dividers Programmable on-chip loop filter Compatible with Spread Spectrum clocks I
Applications
* Low-cost clock source for SERDES ATCA, MicroTCA, AMC, PCI Express Differential Clock Distribution Generic Source Synchronous Clock Management
* Zero-delay clock buffer
* Dynamic Skew Control Through I2C
* Low Output-to-Output Skew (
