ISPCLOCK5300S Datasheet (Lattice Semiconductor) - In-System Programmable Zero-Delay

ISPCLOCK5300S, In-System Programmable Zero-Delay

The ispClock5300S is an in-system-programmable zero delay universal fan-out buffer for use in clock distribution applications.

The ispClock5312S, the ﬁrst member of the ispClock5300S family, provides up to 12 single-ended ultra low skew outputs.

Each pair of outputs may be independently conﬁgured to

ISPCLOCK5300S Features

* Four Operating Conﬁgurations

* Zero delay buffer Zero delay and non-zero delay buffer Dual non-zero delay buffer Non-zero delay buffer with output divider

* Up to +/- 5ns skew range

* Coarse and ﬁne adjustment modes

* Up to Three Cloc