ISP1040B Datasheet | QLogic Corporation

QLogic Corporation ISP1040B Intelligent SCSI Processor Data Sheet Features s s s s s s s s s s s pliance with ANSI SCSI standard X3.131-1994 pliance with ANSI SCSI configured automatically (SCAM) protocol levels 1 and 2 pliance with ANSI X3T10/855D SCSI-3 parallel interface (SPI) standard pliance with ANSI X3T10/1071D Fast-20 standard Onboard RISC processor to execute operations at the I/O control block level from the host memory Supports fast, wide, and Ultra (Fast-20) SCSI data transfer rates SCSI initiator and target modes of operation 32-bit, intelligent bus master, DMA PCI bus interface SCSI operations executed from start to finish without host intervention Simultaneous, multiple logical threads JTAG boundary scan support Product Description The ISP1040B is a single-chip, highly integrated, bus master, SCSI I/O processor for use in SCSI initiator-type applications. The device interfaces the PCI bus to a wide, Ultra SCSI bus and contains an onboard RISC processor. The ISP1040B is a fully autonomous device, capable of managing multiple I/O operations and associated data transfers from initiation to pletion without host CPU intervention. The ISP1040B block diagram is illustrated in figure 1. HOST MEMORY HOST SOFTWARE DRIVER IOCBS REQUEST QUEUE DMA CONTROL RISC REGISTER FILE BOOT CODE MEMORY INTERFACE 32-BIT PCI BUS PCI INTERFACE DATA CHANNEL DATA FIFO WCS MAND FIFO RISC I/O DATA BUS MAND BUFFER MESSAGE BUFFER SXP CODE 8/16-BIT PARALLEL SCSI BUS SEQUENCERS CONTROL REGISTERS SXP SCSI ENGINE FIFO MAILBOX REGISTERS RESPONSE QUEUE CTRL/CONFIG REGISTERS ADDRESS 16 DATA 16 EXTERNAL CODE/DATA MEMORY Figure 1. ISP1040B Block Diagram 83140-580-01 C ..net QLogic Corporation ISP Initiator and Target Firmware The ISP1040B firmware implements a cooperative, multitasking host adapter that provides the host system with plete SCSI mand and data transport capabilities, thus freeing the host system from...