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MACHLV210-12 High Density EE CMOS Programmable Logic

MACHLV210-12 Description

FINAL COM’L: -12/15/20 IND: -18/24 MACHLV210-12/15/20 High Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS s Low-voltage operation, .
The MACHLV210 is a member of the highperformance EE CMOS MACH 2 device family.

MACHLV210-12 Features

* l is chosen, one of two prod

MACHLV210-12 Applications

* s 44 Pins s 64 Macrocells s 12 ns tPD Commercial 18 ns tPD Industrial s 83.3 MHz fCNT Lattice Semiconductor s 38 Bus-Friendly Inputs s 32 Outputs s 64 Flip-flops; 2 clock choices s 4 “PAL22V16” blocks with buried macrocells s Pin-, function-, and JEDEC-compatible with MACH210 s Pin-compatible with

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High Density CMOS Programmable Logic Lattice
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