MACHLV210-12 Datasheet (Lattice) - High Density EE CMOS Programmable Logic

MACHLV210-12, High Density EE CMOS Programmable Logic

The MACHLV210 is a member of the highperformance EE CMOS MACH 2 device family.

This device has approximately six times the logic macrocell capability of the popular PAL22V10 at an equal speed with a lower cost per macrocell.

It is architecturally identical to the MACH210, with the addition of I/O pu

FINAL COM’L: -12/15/20 IND: -18/24 MACHLV210-12/15/20 High Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS s Low-voltage operation, 3.3-V JEDEC compatible VCC = +3.0 V to +3.6 V s < 5 mA standby current s Patented design allows minimal standby current without speed degradation s Exclusively designed for 3.3-V applications s 44 Pins s 64 Macrocells s 12 ns tPD Commercial 18 ns tPD Industrial s 83.3 MHz fCNT Lattice Semiconductor s 38 Bus-Friendly Inputs s 32 Outputs

MACHLV210-12 Features

* l is chosen, one of two prod