OR2C15A Datasheet - Lattice

OR2C15A Field-Programmable Gate Arrays

3 ispLEVER Development System Overview 7 Architecture 7 Programmable Logic Cells 7 Programmable Function Unit 7 Look-Up Table Operating Modes 9 Latches/Flip-Flops 17 PLC Routing Resources 19 PLC Architectural Description 24 Programmable Input/Output Cells 27 Inputs 27 Outputs 28 5 V Tolerant I/O (OR.

OR2C15A Features

* High-performance, cost-effective, low-power 0.35 µm CMOS technology (OR2CxxA), 0.3 µm CMOS technology (OR2TxxA), and 0.25 µm CMOS technology (OR2TxxB), (four-input look-up table (LUT) delay less than 1.0 ns with -8 speed gra

OR2C15A_Lattice.pdf