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MAX3620 Delay Lines

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Description

19-3550; Rev 0; 1/05 Delay Lines for High-Speed Clock Distribution Systems General .
www. Supports HSTL Source Terminated Lines. All-Passive Design. Compatible with 100Ω Differential.

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Features

* Supports HSTL Source Terminated Lines
* All-Passive Design
* Compatible with 100Ω Differential and 50Ω SingleEnded Transmission Lines
* Small 3mm x 3mm Package MAX3620 The MAX3620 series is a family of high-performance passive delay lines for use in QDR/QDRII sync

Applications

* QDR/QDRII Memory Systems Multiphase Clock Generation PART MAX3620AETT MAX3620BETT MAX3620CETT MAX3620DETT Ordering Information TEMP RANGE -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C PIN-PACKAGE 6 TDFN 6 TDFN 6 TDFN 6 TDFN Pin Configuration TOP VIEW IN1 COMMON IN2 1 2 3 6 5 4 OU

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