DSSHA1 Memory-Mapped SHA-1 Coprocessor

Maxim Integrated

Description

DSSHA1 19-5870; Rev 0; 5/11 Memory-Mapped SHA-1 Coprocessor General .
The DSSHA1 coprocessor with 64-byte RAM is a synthesizable register transfer level (RTL) implementation of the FIPS 180-3 Secure Hash Algorithm (SHA-1.

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Datasheet Specifications

Part number: DSSHA1
Manufacturer: Maxim Integrated ↗
File Size: 239.30 KB
Datasheet: DSSHA1-MaximIntegrated.pdf
Description: Memory-Mapped SHA-1 Coprocessor

Features

* SHA-1 Computations Within 670 Clock Cycles (13.4µs at a Typical Frequency of 50MHz)
* Area Estimate is 102,256µm2 in TSMC CL018G (0.18µm Generic Process)
* Dedicated Hardware-Accelerated SHA-1 Engine for Generating MACs
* 64-Byte RAM for Message Input
* Five

DSSHA1 Distributors

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DSSHA1 Memory-Mapped SHA-1 Coprocessor Maxim Integrated

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