MAX9160 Datasheet - Maxim

MAX9160 LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver

The MAX9160 125MHz, 14-port LVTTL/LVCMOS clock driver repeats the selected LVDS or LVTTL/LVCMOS input on two output banks. Each bank consists of seven LVTTL/LVCMOS series terminated outputs and a bank enable. The LVDS input has a fail-safe function. The MAX9160 has a propagation delay that can be ad.

MAX9160 Features

* o LVDS or LVTTL/LVCMOS Input Selection o LVDS Input Fail-Safe Sets Outputs High for Open, Undriven Short, or Undriven Parallel Termination o Two Output Banks with Separate Bank Enables o Integrated Output Series Termination for 60Ω Lines o 200ps (max) Output-to-Output Skew o ±100ps (max) Peak-to-Pea

MAX9160_MaximIntegratedProducts.pdf