Description
Z2V56S20BTP is organized as 4-bank x 16,777,216-word x 4-bit Synchronous DRAM with LVTTL interface and Z2V56S30BTP is organized as 4-bank x 8,388,608-word x 8-bit and Z2V56S40BTP is organized as 4-bank x 4,194, 304-word x 16-bit.
Features
- Z2V56S20BTP, Z2V56S30BTP and Z2V56S40BTP achieve very high speed clock rates up to 166MHz, and are suitable for main memories or graphic memories in computer systems. ITEM
tCLK Clock Cycle Time
(Min. )
CL=2 CL=3
Z2V56S20/30/40BTP
-6 -7 -75 -8
- - 10 10
6 7 7.5
8
tRAS Active to Precharge Command Period (Min. )
42 45
45 48
tRCD Row to Column Delay tAC Access Time from CLK tRC Ref /Active Command Period
(Min. ) (Max. ) (Min. )
CL=2 CL=3
15 20 --
20 6
5 5.4
5.4
60 63 67.5
20 6 6 70
V.
Z2V56S20BTP-Mezza.pdf
