Z2V56S20BTP is organized as 4-bank x 16,777,216-word x 4-bit Synchronous DRAM with LVTTL interface and Z2V56S30BTP is organized as 4-bank x 8,388,608-word x 8-bit and Z2V56S40BTP is organized as 4-bank x 4,194, 304-word x 16-bit.
All inputs and outputs are referenced to the rising edge of CLK.
FEATU
：010-8287 3941/42/43/44 ：010-8287 3945 http://www.echip.com.cn 256Mb Synchronous DRAM Specification Z2V56S20BTP Z2V56S30BTP Z2V56S40BTP Deutron Electronics Corp.
8F, 68, SEC.
3, NANKING E.
RD., TAIPEI 104, TAIWAN, R.
O.
C.
TEL : 886-2-2517-7768 FAX : 886-2-2517-4575 http: // www.deutron.com.tw 256Mb Synchronous DRAM ：010-8287 3941/42/43/44 ：010-8287 3945 http://www.echip.com.cn 256Mb Synchronous DRAMP2V56S20BTP(4-BANKx16,777,216-WORDx4-BIT) P2V56S30BTP (4-BANK x 8,388,608-WORD x 8-BIT) P2V56S4
Z2V56S20BTP Features
* Z2V56S20BTP, Z2V56S30BTP and Z2V56S40BTP achieve very high speed clock rates up to 166MHz, and are suitable for main memories or graphic memories in computer systems. ITEM tCLK Clock Cycle Time (Min.) CL=2 CL=3 Z2V56S20/30/40BTP -6 -7 -75 -8 - - 10 10 6 7 7.5 8 tRAS Active to Precharge Comm
Datasheet Details
Z2V56S20BTP
Mezza
554.10 KB
256mb synchronous dram.
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