SY100E155
FEATURES
750ps max. LEN to output Extended 100E VEE range of
- 4.2V to
- 5.5V 700ps max. D to output Single-ended outputs Asynchronous Master Reset Dual latch-enables Fully patible with industry standard 10KH, 100K ECL levels Internal 75KΩ input pulldown resistors Fully patible with Motorola MC10E/100E155 Available in 28-pin PLCC package
DESCRIPTION
The SY10/100E155 offer six 2:1 multiplexers followed by latches with single-ended outputs, designed for use in new, high-performance ECL systems. The two external latch-enable signals (LEN1 and LEN2) are gated through a logical OR operation before use as control for the six latches. When both LEN1 and LEN2 are at a logic LOW, the latches are transparent, thus presenting the data from the multiplexers at the output pins. If either LEN1 or LEN2 (or both) are at a logic HIGH, the outputs are latched.
The multiplexer operation is controlled by the SEL (Select) signal which selects one of the two bits of input data at each mux to be passed...
