* - Vdd=Vddq=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each po
M2S56D20AKT Datasheet (824.59 KB)
M2S56D20AKT
Mitsubishi
824.59 KB
256m double data rate synchronous dram.
DDR SDRAM (Rev.1.0) Jul. '01 Preliminary M2S56D20/ 30/ 40AKT MITSUBISHI LSIs 256M Double Data Rate Synchronous DRAM PRELIMINARY Some of contents a.
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