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M2V12D20TP-10, M2V Datasheet - Mitsubishi

M2V12D20TP-10 512M Double Data Rate Synchronous DRAM

M2S12D20TP is a 4-bank x 33,554,432-word x 4-bit, M2S12D30TP is a 4-bank x 16,777,216-word x 8-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobes, and output d.

M2V12D20TP-10 Features

* - Vdd=Vddq=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions - Commands are entered on each positive CLK edge; - data and da

M2V-12D.pdf

This datasheet PDF includes multiple part numbers: M2V12D20TP-10, M2V. Please refer to the document for exact specifications by model.
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Datasheet Details

Part number:

M2V12D20TP-10, M2V

Manufacturer:

Mitsubishi

File Size:

754.04 KB

Description:

512m double data rate synchronous dram.

Note:

This datasheet PDF includes multiple part numbers: M2V12D20TP-10, M2V.
Please refer to the document for exact specifications by model.

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M2V12D20TP-10 M2V 512M Double Data Rate Synchronous DRAM Mitsubishi

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