* - Vdd=Vddq=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions - Commands are entered on each positive CLK edge; - data and da
M2V12D20TP-75L Datasheet (754.04 KB)
M2V12D20TP-75L
Mitsubishi
754.04 KB
512m double data rate synchronous dram.
DDR SDRAM (Rev.1.1) Feb.ELECTRIC '02 MITSUBISHI MITSUBISHI LSIs M2S12D20/ 30TP -75, -75L, -10, -10L 512M Double Data Rate Synchronous DRAM DESCRIPT.
📁 Related Datasheet
M2V12D20TP-75 512M Double Data Rate Synchronous DRAM (Mitsubishi)
M2V12D20TP-10 512M Double Data Rate Synchronous DRAM (Mitsubishi)
M2V12D20TP-10L 512M Double Data Rate Synchronous DRAM (Mitsubishi)
M2V12D20TP 512M Double Data Rate Synchronous DRAM (Mitsubishi)
M2V12D30TP 512M Double Data Rate Synchronous DRAM (Mitsubishi)
M2V12D30TP-10 512M Double Data Rate Synchronous DRAM (Mitsubishi)
M2V12D30TP-10L 512M Double Data Rate Synchronous DRAM (Mitsubishi)
M2V12D30TP-75 512M Double Data Rate Synchronous DRAM (Mitsubishi)
M2V12D30TP-75L 512M Double Data Rate Synchronous DRAM (Mitsubishi)
M2V28D20ATP-10 128M Double Data Rate Synchronous DRAM (Mitsubishi)
