* - Single 3.3v±0.3v power supply - Clock frequencies of 125 MHz - Fully synchronous operation referenced to clock rising edge - Dual bank operation controlled by A10(Bank Address) - Internal pipelined operation: column address can be changed every clock cycle - Programmable /CAS Latency (LVTTL: 2 and
M5M4V16G50DFP-12 Datasheet (167.55 KB)
M5M4V16G50DFP-12
Mitsubishi
167.55 KB
16m (2-bank x 262144-word x 32-bit) synchronous graphics ram.
SGRAM (Rev. 0.0) Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V16G50DFP -8, -10, -12
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
PRELIM.
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