* - Single 3.3v±0.3v power supply - Clock frequency 125MHz / 100MHz / 83MHz - Fully synchronous operation referenced to clock rising edge - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8 (programmable) - Burst type- sequential / interl
M5M4V64S20ATP-12 Datasheet (1.07 MB)
M5M4V64S20ATP-12
Mitsubishi
1.07 MB
64m (4-bank x 4194304-word x 4-bit) synchronous dram.
SDRAM (Rev.0.2) Jan'97 Preliminary
MITSUBISHI LSIs
M5M4V64S20ATP-8, -10, -12
64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
PRELIMINARY
Some.
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