M5M4V64S20ATP-12, M5M - 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM

Mitsubishi

Datasheet Details

Part number	M5M4V64S20ATP-12, M5M
Manufacturer	Mitsubishi
File Size	1.07 MB
Description	64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
Datasheet	M5M-4V6.pdf
Note	This datasheet PDF includes multiple part numbers: M5M4V64S20ATP-12, M5M. Please refer to the document for exact specifications by model.

The M5M4V64S20ATP is a 4-bank x 4194304-word x 4-bit Synchronous DRAM, with LVTTL interface.

- Single 3.3v±0.3v power supply - Clock frequency 125MHz / 100MHz / 83MHz - Fully synchronous operation referenced to clock rising edge - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8 (programmable) - Burst type- sequential / interleave (programmable) - Column access - random - Auto precharge / All bank precharge controlled by A10 - Auto refresh and Self refresh - 4096 refresh cycles /64ms - Column address A0-A9 - LVTTL Interfac.

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Other Datasheets by Mitsubishi

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Published: Apr 26, 2005 |