DSP56857 - 120 MIPS Hybrid Processor
* 120 MIPS at 120MHz * 40K x 16-bit Program SRAM * 24K x 16-bit Data SRAM * 1K x 16-bit Boot ROM * Six (6) independent channels of DMA * Two (2) Enhanced Synchronous Serial Interfaces (ESSI) * Two (2) Serial Communication Interfaces (SCI) <
DSP56857 Features
* 1.1.1
* Digital Signal Processing Core Efficient 16-bit engine with dual Harvard architecture 120 Million Instructions Per Second (MIPS) at 1
