SN54LS73A Datasheet (Motorola Inc) - DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

SN54LS73A, DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

SN54/74LS73A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54LS / 74LS73A offers individual J, K, clear, and clock inputs.

These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted.

The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum set-up times are observed.

Input data is transferred to the outputs on the negative-go