MC68EC040 Datasheet - Motorola Semiconductor

MC68EC040 Microprocessor

of table descriptors. 0 = Read and write accesses permitted. 1 = Write accesses not permitted. B.3.2 Address Comparison The following description of address comparison assumes that the ACRs are enabled. Clearing the E-bit in each ACR independently disables access control, causing the processor to i.

w w S a t APPENDIX B a MC68EC040 .D w e e h U 4 t m o .c REV2.2 (11/02/99) NOTE Rev. 2.2 contains timing information for 40 MHz operation. Refer to chang bars. Some TBD values will be filled in shortly. All references to MC68EC040 also apply to the MC68EC040V. Refer to Appendix C MC68040V and MC68EC040V for more information on the MC68EC040V. The MC68EC040 is Motorola's third generation of M68000-compatible, high-performance, 32-bit microprocessors. The MC68EC040 is an embedded control.

MC68EC040 Features

* of the MC68EC040 include:

* MC68040-Compatible Integer Execution Unit

* 4-Kbyte Instruction Cache and 4-Kbyte Data Cache Accessible Simultaneously

* 32-Bit, Nonmultiplexed External Address and Data Buses with Synchronous Bursting Interface

* User-Object-Code Compatibl

MC68EC040 Datasheet (116.75 KB)