Description
On-Chip Cache Memory Bus Operation Exception Processing Coprocessor Interface Description Instruction Execution Timing Applications Information Electrical Characteristics Ordering Information and Mechanical Data Interfacing an MC68EC020 to a DMA Device That Supports a Three-Wire Bus Arbitration Protocol NOTE In this manual, assert and negate are used to specify forcing a signal to a particular state.
Features
- 1-2 Programming Model 1-4 Data Types and Addressing Modes Overview 1-8 Instruction Set Overview  1-10 Virtual Memory and Virtual Machine Concepts  1-10 Virtual Memory  1-10 Virtual Machine  1-12 Pipelined Architecture 1-12 Cache Memory 1-13 Section 2 Processing States 2.1 2.1.1 2.1.2 2.1.3 2.2 2.3 2.3.1 2.3.2 Privilege Levels  2-2 Supervisor Privilege Level 2-2 User Privilege Level 2-3 Changing Privilege Level  2-3 Address Space Types 2-4 Exception Processing 2-5 Exception Vectors 2-5 Exception.