MC100E256 Datasheet - Motorola

MC100E256 3-BIT 4:1 MUX-LATCH

MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3ĆBit 4:1 MuxĆLatch The MC10E/100E256 contains three 4:1 multiplexers followed by transparent latches with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs (see logic symbol). When the Latch Enable (LEN) is LOW, the latch is transparent, and output data is controlled by the multiplexer select controls. A logic HIGH on LEN latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LO.

MC100E256 Datasheet (109.76 KB)