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MC14516B - Binary Up/Down Counter

Features

  • CK P0 P1 P2 P3 Q2 Figure 1. Power Dissipation Test Circuit and Waveform LOGIC.

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Full PDF Text Transcription

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC14516B Binary Up/Down Counter The MC14516B synchronous up/down binary counter is constructed with MOS P–channel and N–channel enhancement mode devices in a monolithic structure. This counter can be preset by applying the desired value, in binary, to the Preset inputs (P0, P1, P2, P3) and then bringing the Preset Enable (PE) high. The direction of counting is controlled by applying a high (for up counting) or a low (for down counting) to the UP/DOWN input. The state of the counter changes on the positive transition of the clock input. Cascading can be accomplished by connecting the Carry Out to the Carry In of the next stage while clocking each counter in parallel.
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